The most common display mode used in display systems, such as personal computers or display adapters for such computers, comprises the "indirect color mode." In this operational mode, picture element (or pixel) data contained in a display memory array is accessed to define the primary color intensity values of pixels to be displayed.
In a display system having an all-points addressable (APA) display memory, multiple bits are stored for each pixel of a display field corresponding, for example, to the screen of a display device. When operating in indirect color mode, these bits in the display memory form an index for accessing a location within a look-up table called a palette. The addressable locations in the palette contain display data defining the primary color intensity of a pixel having an index addressing that pixel palette location.
In the case of a display system controlling a color cathode ray tube (CRT), or other display device where colors are generated by mixing the primary colors red, green and blue, the pixel palette entry will contain intensity values for each primary color. If the display device requires analog signals for controlling the physical display processes, the intensity data output from the pixel palette are converted into analog signals by digital-to-analog converters (DACs) for controlling the display device, e.g., in the case of a color CRT, the color guns.
In indirect color mode, it is usual for up to eight bits to be stored for each pixel in a display memory and for these bits to be translated in a look-up table, or pixel palette, into three values which define the intensity of the red, green and blue components of the pixel. Today's standard indirect color mode is for the palette to generate eight bits each for red, green and blue, making 24 bits in all. Where the display memory comprises eight bit planes (i.e., 8 bits-per-pixel), it allows the simultaneous display of up to 256 different colors chosen from 16.8 million possible colors.
In certain other applications, referred to as "direct color mode," a pixel color may be specified directly. Conventionally, in this mode the values stored in the display memory control the display device directly via the DACs. Today's systems typically operate in either an indirect color mode, via pixel palettes, or a direct color mode, via a palette bypass. Additionally, SPD devices often support an overlay palette and a cursor palette for implementing an "overlay color mode" and a "cursor color mode," respectively. Thus, the ultimate display data fed to the DACs comprises 24 pixel data bits, consisting of eight bits for each primary color coming from four potential data sources, i.e., the pixel palettes, palette bypass, overlay palette and cursor palette. A major problem encountered when designing an SPD device is thus the complexity of the multiple display data paths that converge on a final multiplexer en route to the DACs. The problem is greatly magnified because the circuitry involved is typically running at pixel frequencies, e.g., frequencies in excess of 200 MHz, resulting in significant design challenges.
Between any two consecutive latch stages, logic and data flow functions cannot have large path delays because of the very short clock periods involved. This implies that complex logic or data flow operations must be spread over several latched stages in a "pipeline." Since all display data and data flow control must arrive synchronized to correctly generate the required display data, all paths must be the same length and therefore simple paths must be "padded" to match the length of the longest, most complex path. This results in significantly increased cell-counts, with even greater penalties incurred at higher pixel frequencies.
Large cell counts operated at very short clock periods significantly challenges the physical design and layout of the circuit's critical nets. To meet stringent, imposed timing criteria, a major effort must be expended in placement, floor planning and custom wiring stages of the design effort. Further, to ensure success, additional analysis and design interaction is often required, resulting in added design time and increased cell-count.
The present invention addresses these problems by providing an enhanced, memory structure having multiple, distinct memory array portions integrated together in a single macro which, for example, can be designed for an SPD device to accommodate indirect color mode, direct color mode, overlay color mode and cursor color mode processings to significantly improve data path timings and provide a cleaner logic interface compared with standard SPD device implementations.